1. Field of the Invention
The present invention relates to a semiconductor device and an operation thereof, and more particularly to a semiconductor device including a non-volatile memory and an operation thereof.
2. Description of the Related Art
NAND type EEPROMs (electrically erasable programmable read only memory) are popular as semiconductor devices which include electrically programmable and erasable non-volatile memories. FIG. 19 to FIG. 23 of the accompanying drawings show a structure of such a NAND type EEPROM, and FIG. 24 shows a circuit configuration of the NAND type EEPROM.
In the NAND type EEPROM, a memory array 100 is constituted by a plurality of memory cell units 101 arranged in the shape of a matrix. Each memory cell unit 101 includes eight memory cells 102 which are connected in series in a row. Generally speaking, the memory cell 102 can store 1-bit data while the memory cell unit 101 can store 1-byte data.
Referring to FIG. 21 to FIG. 23, the NAND type EEPROM is provided on a main surface of a semiconductor substrate 110 (i.e. a semiconductor chip), which is made of a silicon single crystal substrate. A plurality of memory cells 102 are positioned on the main surface (a well region, not shown) of the semiconductor substrate 110. The memory cells 102 are surrounded by an element isolate insulating film 111 at a gate width regulating area.
Each memory cell 102 includes: a channel forming region (the semiconductor substrate 110 or the well region); a first gate insulating film 121; a floating gate electrode (charge storing section) 122 on the first gate insulating film 121; a second gate insulating film 123 on the floating gate electrode 122; a control gate electrode 124 on the second gate insulating film 123; and a pair of semiconductor regions 125 functioning as source and drain regions. In other words, each memory cell 102 is constituted by an n-channel conductivity type field effect transistor including the floating gate electrode 122. In the memory cell unit 101, the semiconductor regions 125, i.e. a source or drain region, of one memory cell 102 in a row are integral with semiconductor regions 125 of another memory cell 102 which is adjacent in the same row. Referring to FIG. 19 and FIG. 22, the control gate electrode 124 of one memory cell 102 in a column is integral with a control gate electrode 124 of another memory cell 102 which is adjacent in the same column, thereby constituting a word line 124WL extending in the column and the row.
A cell selecting transistor 105 is provided for the memory cells 102 at one end of the memory cell unit 101 (i.e., at the upper part in FIG. 19, and at the left side in FIG. 23). Further, a cell selecting transistor 106 is provided for the memory cell at the other end of the memory cell unit 101 (i.e., at the lower part in FIG. 19, and at the right side in FIG. 23).
The cell selecting transistors 105 and 106 are n-channel conductivity type field effect transistors. The cell selecting transistor 105 includes a channel forming region, a gate insulating film 151 on the channel forming region, a gate electrode 152 on the gate insulating film. 151, and a pair of n-channel type semiconductor regions 155 functioning as a source or drain region. The gate electrode 152 is integral with a gate electrode 152 of an adjacent cell selecting transistor 105 in the same column, thereby constituting a cell selecting signal line 152S.
The cell selecting transistor 106 includes a channel forming region, a gate insulating film 161 on the channel forming region, a gate electrode 162 on the gate insulating film 161, and a pair of n-channel type semiconductor regions 165 functioning as a source or drain region. The gate electrode 162 is integral with a gate electrode 162 of an adjacent cell selecting transistor 106 in the same column, thereby constituting a cell selecting signal line 162S.
On the memory cell unit 101, a plurality of bit lines 136 are provided in the column and extend in the row which intersects the word line 124WL. A plurality of sub-bit lines 133 under the bit lines 136 are connected to the semiconductor regions 155 via connecting hole wirings 131. The sub-bit lines 133 are formed on a first wiring layer of an inter-level isolation layer 130. The bit lines 136 are formed on a second wiring layer of an inter-level isolation layer 135 extending over the sub-bit lines 133. The bit lines 136 are connected to the semiconductor region 155 at one end of the cell selecting transistor 105 via the sub-bit lines 133 and connecting hole wirings 131.
Source lines 134 are provided on the first wiring layer of the inter-level isolation film 130 together with the sub-bit lines 133, and are connected via the connecting hole wiring 132 to one of the semiconductor regions 165 of the cell selecting transistor 106.
FIG. 25 to FIG. 27 show a structure of another NAND type EEPROM, which has essentially a circuit configuration identical to that shown in FIG. 24, but does not include sub-bit lines 133. Specifically, bit lines 136 are provided on a first wiring layer of an inter-level isolation film 130, and are connected to one of semiconductor regions 155 of a cell selecting transistor 105 via a connecting hole wiring 131. This NAND type EEPROM does not include source lines 134 but is provided with source lines 165S integral with one of semiconductor regions 165 of an adjacent cell selecting transistor 106 in the same column.
Operations of the foregoing NAND type EEPROMs will be described with reference to FIG. 28.    (1) First of all, existing data are erased in a memory cell array 100 of the NAND type EEPROM. Specifically, the data are simultaneously erased from the memory cells 102 in a selected memory block. For this purpose, 0V is applied to the control gate electrode 124 (the word line 124WL) while a high voltage VPPW, e.g. 20V, is applied to the semiconductor substrate (well region) 110. An FN tunnel current flows to the first gate insulating film 121, and electrons are discharged from the floating gate electrode (charge storing section) 122 to the semiconductor substrate 110, so that a threshold voltage of the memory cell 102 becomes negative.    (2) Thereafter, data are written (step 170S) into the memory cells 102 connected to one word line 124WL. Specifically, the data are separately written into the memory cells 102 connected to even-numbered bit lines 136 (e.g. BL2, BL4, . . . ) and into the memory cells 102 connected to odd-numbered bit lines 136 (e.g. BL1, BL3, . . . ). For instance, the data are simultaneously written into a plurality of even-numbered memory cells 102 connected to the selected word line 124WL.
In order to write data “0” in the memory cells 102, i.e. in order to make the threshold voltage thereof positive, 0V is applied to the bit lines 136. On the other hand, in order to write data “1” in the memory cells 102, i.e. in order not to change the threshold value thereof, a writing voltage VCC, e.g. 3V, is applied to the bit lines 136. When writing data in the memory cells 102 connected to even-numbered bit lines 136, the writing voltage VCC is applied to odd-numbered bit lines 136. Further, the writing voltage VCC is applied to the cell selecting signal lines 152S connected to the cell selecting transistor 105, and a writing voltage VPASS, e.g. 10V, is applied to non-selected word lines 124WL. Still further, a high writing voltage VPPW, e.g. 20V, is applied as pulses to the selected word line 124WL (step 171S).
In the memory cells 102 where data “0” is to be written, 0V is applied to the drain region (semiconductor region 125), the channel forming regions, and the source regions (semiconductor region 125), and a high voltage is applied between the channel forming regions and the control gate electrodes 124. Therefore, the FN tunnel current flows to the first gate insulating film 121, and electrons are introduced into the floating gate electrodes 122. Therefore, the threshold voltage of the memory cells 102 is made positive.
On the other hand, in the memory cells 102 where data “1” is to be written, the cell selecting transistors 105 are in a cutoff state. The potential of the channel forming regions is raised because of coupling capacitance caused by the voltage VPASS to the non-selected control gate 124, so that a moderate electric field is generated between the channel forming region and the control gate electrodes 124. Since no electrons are introduced to the floating gate electrodes 122 from the channel forming regions, the threshold voltage of the memory cells 102 does not change.
Further, the threshold voltage of the memory cells 102 connected to the odd-numbered bit lines 136 does not change while the data are being written into the memory cells 102 connected to the even-numbered bit lines 136.    (3) Once the high wiring voltage VPPW is applied to the selected word line 124WL, verification is performed in order to check the threshold voltage of the memory cells 102 where data “0” has been written has reached a specified value (step 172S). For this purpose, the reading voltage VCC, e.g. 3V, is applied to the even-numbered bit lines 136, 0V is applied to the odd-numbered bit lines 136, 0V is applied also to the control gate electrode 124 (the word line 124WL) connected to the selected memory cells 102, and the reading voltage VCC is applied to other word lines 124WL and cell selecting signal lines 152S. Further, it is also verified whether or not a current flows from the bit lines 136 via the memory cells 102 during the application of the verifying voltage. If the current flows in this state, the threshold voltage of the selected memory cells 102 does not become high enough, i.e. the data writing has not been completed. In such a case, the data writing will be repeated.
Conversely, when no current flows, the data writing has been completed. The 0V at the bit lines 136 is switched over to the voltage VCC, thereby prohibiting further data writing, and preventing the threshold voltage from varying in the memory cells 102.
Thereafter, the data will be repeatedly and similarly written into all of the memory cells 102 connected to the selected word lines 124WL and the odd-numbered bit lines 136 (step 173S).    (4) In the similar manner, the data will be written into the memory cells 102 connected to the odd-numbered bit lines 136 (steps 175S and 176S). The written data are verified (step 177S). Further, the data are repeatedly written into all of the memory cells 102 connected to the selected word line 124WL and the odd-numbered bit lines 136 (178S).    (5) The data will be read in the manner similar to that of the verification. The reading voltage VCC, e.g. 3V, is applied to the bit lines 136, 0V is applied to the control gate electrode 124 (word line 124WL) connected to the selected memory cells 102, and the reading voltage VCC is applied to other word lines 124WL and cell selecting signal lines 152. Thereafter, it is checked whether or not a current flows from the bit lines 136 via the memory cells 102. Similarly to data writing, data reading is separately performed for the memory cells 102 connected to the even-numbered bit lines 136 and for the memory cells 102 connected to the odd-numbered bit lines 136. When reading the data from the memory cells 102 connected to the even-numbered bit lines 136, 0V is applied to the odd-numbered bit lines 136. Conversely, in order to read the data from the memory cells connected to the odd-numbered bit lines 136, 0V is applied to the even-numbered bit lines 136.
Therefore, it is possible to prevent erroneous data reading due to interference between adjacent bit lines in a row through separate data reading for the memory cells 102 connected to the odd- and even-numbered bit lines 136, respectively, as will be described hereinafter.
During the data reading, the bit lines 136 are charged, and the non-selected control gate electrodes 124 and non-selected word lines 124WL are activated. The data are recognized depending upon whether the charged voltage is lowered in the bit lines 136. Specifically, if the charged voltage is lowered, the data “0” is recognized. If not, data “1” is recognized.
The following describe how the data are read from the memory cells 102 without dividing them into those connected to the even-numbered and odd-numbered bit lines 136. It is assumed here that, as shown in FIG. 29, the bit lines 136 (BL1, BL2, and BL3) are juxtaposed, and data “0” has been stored in the memory cells 102 connected to the bit lines 136 (BL1 and BL3) while the data “1” has been stored in the memory cell 102 connected to the bit line (BL2).
During the data reading, the charging potential of the bit lines 136 (BL1 and BL3) should be ideally lowered while the charging potential of the bit line 136 (BL2) should ideally remain unchanged. There is coupling capacitance CBL12 between the adjacent bit lines 136 (BL1 and BL2) while there is coupling capacitance CBL23 between the adjacent bit lines 136 (BL2 and BL3). If the charging potential is lowered at the bit lines 136 (BL1 and BL3), the charging potential of the bit line 136 (BL2) is slightly lowered due to coupling noises. As a result, the data stored in the memory cells 102 connected to the bit line 136 (BL2) would be erroneously recognized to be data “1”. Further, the more micro spaces between the bit lines 136, the more coupling noises would be increased, and the more remarkable the erroneous data reading.
The following reference is known in order to effectively overcome the foregoing problems of the related art: “A Quick Intelligent Page-Programming Architecture and a Shielded Bit line Sensing Method for 3V-only NAND Flash Memory”, by T. Tanaka, et al., (IEEE J. Solid-State Circuits, vol. 29, no. 11, pp. 1366-1378, November 1994). In this bit line shielding technique, each second bit line is read during page programming, and bit lines which are not read are grounded, thereby reducing coupling noises.
With the foregoing NAND type EEPROMs, it is possible to reduce coupling noises between adjacent bit lines by utilizing the bit line shielding technique, but the following problems seem remain unsolved.    (1) The more micro-fabricated NAND type EEPROMs, the more reduced spaces between floating gate electrodes 122 of adjacent memory cells 102. Therefore, the coupling capacitance between the floating gate electrodes 122 tends to become more influential. Referring to FIG. 30, the coupling capacitance CFGR is produced between the floating gate electrodes 122 of adjacent memory cells 102 in the same row. Further, the coupling capacitance CFGC is produced between the floating gate electrodes 122 of adjacent memory cells 102 in the same column, as shown in FIG. 31.
If a threshold voltage of a memory cell 102 which is adjacent to a particular memory cell 102 varies, a threshold voltage of the particular memory cell 102 seems to increase in response to the coupling capacitances CFGR and CFGC. For instance, if the threshold voltage of the adjacent memory cell 102 becomes negative from positive, the threshold voltage of the particular memory cell 102 seems to become positive in response to this change. In other words, when the data writing is separately performed for the memory cells 102 connected to the even-numbered bit lines 136 and the memory cells 102 connected to the odd-numbered bit lines 136, the threshold voltage of the memory cell 102 where the data are written first will be affected by the coupling capacitances CFGR and CFGC, and seems be changed in response to the threshold voltage of the memory cell 102 where the data are written later.
It is assumed here that the data are written into a memory cell 102 connected to an even-numbered bit line 136 at first and that data “0” is written into the particular memory cell 102. A threshold voltage of an adjacent memory cell 102 connected to an odd-numbered bit line 136 is negative (remains the same as that during the erasing). When data “0” is written into memory cells 102 which are connected to odd-numbered bit lines 136 and adjacent to the particular memory cell 102 on the opposite sides thereof (i.e. threshold voltages of the adjacent memory cells 102 are changed to positive from negative), the threshold voltage of the particular memory cell 102 is changed to positive in response to the coupling capacitances CFGR and CFGC.
Variations of the threshold voltages of the memory cells 102 will result in variations of threshold voltages after the data writing, and cause erroneous operations of the NAND type EEPROMs. Further, there is a problem that along with the micro-fabrication, coupling capacitances between the floating gate electrodes 122 of adjacent memory cells 102 become serious not only in matrixes (in rows and columns) but also diagonally, which means that erroneous operations are also serious in the NAND type EEPROMs.    (2) In order to increase a storage capacity per memory cell, multiple-valued memory cells are being developed for NAND type EEPROMS, AND type EEPROMs and so on. With the multiple-valued memory cell, the threshold voltage is divided into four levels (quadruple) in place of two levels (binary), thereby increasing the storage capacity. The storage capacity and integration degree of the quadruple memory cell are doubled compared with those of binary memory cells. Needless to say, variations of threshold voltages after data writing should be reduced in order to realize multiple-value memory cells.
However, it has been very difficult to realize multiple-valued memory cells because coupling capacitances become strong between floating gate electrodes of adjacent memory cells as memory cells are being micro-fabricated, and because it is difficult to reduce variations of threshold voltages after data writing.